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EP1810LC-45 - The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
Description:
The Altera ClassicTM device family offers a solution to high-speed, low-power logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet.
Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages.
Applications:
Macrocells
Programmable registers
Output enable/clock select
Feedback select
Specifications:
| part no. | EP1810LC-45 | ||
| Manufacturer | ALTERA | ||
| supply ability | 4500 | ||
| datecode | 07+ | ||
| package | PLCC68 |  Sell
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